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====== Virtex-7 Dynamic Tests campaign (2016-2017) ====== 
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===== Test dates =====
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  * ** [[data_analysis:v7-dynamic:201612-tamu| 2016.12 TAMU ]] ** 
  * ** [[data_analysis:v7-dynamic:201701-ucd| 2017.01 UCD ]] ** 
  * ** [[data_analysis:v7-dynamic:201703-tamu| 2017.03 TAMU ]] ** 

V7 microlatchup: 1.26v is POR for Vccaux - so POR trips (absolutely authoritative source, originally responsible designer of the circuitry)
HRIO use 180nm fets, or 1.8v devices so HRIO use a cascade (two p fet in series, two n fet in series in a stacked set of CMOS for pre-drivers, logic, level shifters, and drivers to the up to 3.3v IO pin.

if you remember we talked about that possibility (triggering PO/brownout reset) time ago.
Carefully lowering the voltage to ~1.2V gets rid of the extra current, but does not kick off housekeeping like clearing the CRAM; design is there when we'd raise the voltage to nominal and check CRAM with ConfigMon.
So, could not be POR